Power-On-Reset (POR) circuits are widely used throughout the electronics industry to hold microprocessor based systems in a "reset" mode, i.e., with a ground at the processor's RESET input, during power on and off transitions and other conditions when the logic voltage, typically 5 volts, is invalid.
Common and recurring problems with present day POR circuits relate to transients, or "glitches," on the POR output, missing POR signals, POR outputs not present when precisely required, and unwanted or multiple POR signals. These problems often result from inadequate circuit designs, accuracy errors in detecting precision threshold levels for valid logic power, propagation delay errors in generating the POR output, and slow rise and fall POR transition times.
Comparators are commonly used to monitor the logic supply voltage and to generate the POR output. The basic problem with this approach is that with no power applied to the circuit, a comparator (having an open collector) has no supply voltage and, therefore, cannot always output the proper (ground) POR signal. When power is applied, a minimum supply voltage is required before the comparator can begin to operate properly. This results, as depicted in FIG. 1(a), in an inherent "glitch" 10 during turn-on. FIG. 1(b) shows the supply voltage 12 gradually being turned-on from a turned-off condition 14. FIG. 1(c) shows the logic voltage 16 rising concurrently. A POR signal 18 is shown properly occurring, in FIG. 1(a), when the logic voltage 16 rises to a selected valid level 20, as shown in FIG. 1(c). The "glitch" 10 condition occurs while the collector is still open, before the supply voltage is high enough to cause the comparator to operate properly. Such a "glitch" is totally unacceptable in multiple channel systems where one channel monitors the POR status of another channel.
Most present day POR circuits require a turn-on time delay to allow the logic supply to turn on and stabilize within its regulation band before the POR enable signal is generated. However, at turn-off, a time delay is not desirable since POR must be generated immediately in order to prevent the processor from operating during invalid power conditions.
FIGS. 2 and 3 show prior art designs presently being used in an attempt to meet these delay requirements. The intent of the circuit of FIG. 2 is to provide a long time constant using a resistor 22 and a capacitor 24 when the 5 V logic on a line 26 is turned on (to delay the POR ground output on a line 28 from a comparator 30 from being removed too soon), and to provide a short time constant using a resistor 32 and capacitor 24 through a diode 34 when the 5 V logic on line 26 is turned off (in order to immediately apply a POR output ground when logic power becomes invalid). The problem with this circuit is that the voltage drop across diode 34 must exceed 0.7 V before the discharge path from capacitor 24 through resistor 32 can begin to conduct. This introduces an error of 0.7 V in the 5 V valid logic trip level which results in the microprocessor based system operating with invalid power.
The circit of FIG. 3 solves some of the problems related to that of FIG. 2. However, it creates new problems. When the POR output on a line 35 transitions from ground to open, a capacitor 36 charges to 5 V through a resistor 38, providing the desired time delay. However, the POR rising edge is slow, which is undesirable for good noise immunity and may produce "glitches" by not meeting the rise time requirements of the interface circuits. Also, the reliability of a comparator 40 is degraded due to being over stressed from high peak discharge currents from capacitor 36 each time the POR output is switched to ground.
Another approach to glitch problems is to buffer the output of the comparator with an n-channel, junction field effect transistor (JFET). The n-channel JFET is a "normally-on" device which means that, with no power applied to the circuit, the drain to source resistance is normally low, providing a valid POR signal. Since the n-channel JFET requires a negative gate voltage for "pinch-off" and since negative voltages are not generally available from the power bus, a negative bias voltage must be generated from the system's power supply. This presents a race condition during system power cycling. At turn-on, the negative bias voltage required for pinch-off and the positive supply voltage required to bias the comparator must race the logic supply to ensure that the comparator is operational before the logic supply becomes valid. At turn-off, the positive and negative bias supplies must remain operational until the logic supply becomes invalid. Variation in the logic loading will vary the time required for the logic supply to become valid and further complicate the race.